Applied Methods
~The MetaPhysical SystemsChip & Silicon Engineer

Chip & Silicon Engineer

Chip & Silicon Engineers at AI companies work across the chip-design lifecycle for AI accelerators and supporting silicon—from RTL and microarchitecture through physical design, verification, and post-silicon validation. The role spans front-end design (architecting blocks, writing RTL, running simulation), physical design (synthesis, place-and-route, timing closure, power-performance-area optimization), and post-silicon work (bring-up, characterization, debug across hardware, firmware, and software layers). Specialization within this slug varies—some engineers focus narrowly on one phase of the pipeline, others coordinate across phases—but the population spans the full chain rather than concentrating on any single stage. These engineers typically sit within silicon, hardware, or platform engineering organizations at chip-focused AI companies, collaborating closely with verification, software, and systems teams to deliver production silicon.

$ titles --canonical
SoC ArchitectRTL Design EngineerPhysical Design EngineerSilicon Verification EngineerASIC Design EngineerFPGA EngineerPost Silicon Validation EngineerAdvanced Packaging TechnologistSilicon Emulation EngineerStaff SoC ArchitectAI Silicon Physical Design Engineer
Open Jobs54
Companies Hiring7
$02

Skills

What companies are looking for in this role.

$ skills --core

Optimizing silicon designs for power, performance, area, and cost tradeoffs

95%

Performing physical design tasks including synthesis, place and route, and timing closure

95%

Conducting post-silicon validation and verification across hardware, firmware, and software domains

93%

Performing silicon bring-up and characterization of new chips on bench platforms and evaluation boards

93%

Developing microarchitecture and RTL to implement chip architecture specifications

92%

Defining and executing bring-up and characterization plans for silicon devices in production systems

92%

Debugging and resolving complex issues across silicon, firmware, and system interactions

92%

Developing test infrastructure, scripts, and tools to validate silicon functionality

90%

Executing block-level and full-chip physical verification methodology

90%

Leading system validation strategy and execution for blade and rack-level platforms

88%

Designing and architecting system-on-chip solutions from concept through production delivery

88%

Building and maintaining automated test infrastructure and lab instrumentation setups

88%

Performing automated and manual testing in laboratory and data center environments

87%

Conducting circuit-level optimization and implementation-driven power, performance, and area optimization

85%

Integrating intellectual property and subsystems into top-level system designs

85%

Architecting energy-efficient machine learning accelerator compute subsystems for inference workloads

85%

Performing hardware and software co-design to maximize performance per watt and system efficiency

82%

Analyzing silicon data and identifying gaps between design goals and actual silicon performance

82%

Collaborating with foundry partners to optimize process technology and design libraries

80%
$ skills --emerging

Evaluating and integrating emerging semiconductor technologies including advanced packaging and three-dimensional integration

72%

Using artificial intelligence tools and automation to accelerate silicon design and implementation workflows

70%

Applying machine learning techniques to silicon validation and test data analysis

65%
$ skills --soft

Collaborating effectively across architecture, hardware, software, and systems engineering teams

90%

Leading cross-functional teams in silicon design, verification, and validation efforts

85%

Driving root cause analysis and issue resolution through cross-domain debugging

85%

Translating product requirements into scalable silicon architecture solutions

80%

Communicating technical requirements and design specifications across distributed engineering teams

80%

Managing execution against aggressive program schedules and milestones

78%

Mentoring and developing high-performing engineering teams in design and validation

75%
$03

Technology

The tools and technologies that define this role.

$ tech --language
Pythonhigh
SystemVeriloghigh
Veriloghigh
Cmoderate
C++moderate
SystemCmoderate
VHDLmoderate
Chisellow
$ tech --framework
UVMhigh
OpenVINOlow
PyTorchlow
TensorFlowlow
$ tech --platform
Physical Design Automationvery high
Linuxhigh
TSMChigh
ARMmoderate
Dockermoderate
FPGAmoderate
Intel Foundrymoderate
Samsung Foundrymoderate
CUDAlow
GlobalFoundrieslow
RISC-Vlow
$ tech --tool
Cadencevery high
Synopsysvery high
SPICEhigh
VCShigh
Gitmoderate
HLSmoderate
Jenkinsmoderate
Memory Compilermoderate
Mentor Graphicsmoderate
ModelSimmoderate
Questamoderate
Xceliummoderate
ASMLlow
Riviera-PROlow
Vivadolow
$ tech --concept
Inferencevery high
Static Timing Analysisvery high
Clock Domain Crossinghigh
Design for Testhigh
Design Rule Checkinghigh
Machine Learninghigh
Reset Domain Crossinghigh
3D Integrationmoderate
Advanced Packagingmoderate
AXImoderate
Ethernetmoderate
FinFETmoderate
Formal Verificationmoderate
High-Level Synthesismoderate
JTAGmoderate
PCIemoderate
Power Distribution Networkmoderate
Thermal Analysismoderate
Trainingmoderate
GAA FETlow
Silicon Photonicslow
$04

Open Jobs

54 open Chip & Silicon Engineer jobs across 7 companies.

Graphcore5d
Senior System Validation Engineer
Austin, Texas, United States·Physical Systems
Graphcore5d
Staff System Validation Engineer
Austin, Texas, United States·Physical Systems
Graphcore5d
Technical Lead - System Validation Architect
Austin, Texas, United States·Physical Systems
Graphcore1w
Hardware Validation and Debug Engineer - DDR
Bristol, UK·Physical Systems
Graphcore1w
Graduate SoC Architect
Bristol, UK·Physical Systems
OpenAI2w
Physical Design Engineer, Forward Deployed Engineering
San Francisco·Physical Systems
Graphcore2w
Principal Silicon Verification Engineer - Bengaluru
Bengaluru, India·Physical Systems
Cerebras Systems2w
Sr. Technical Staff
Sunnyvale, CA·Physical Systems
Graphcore2w
Senior Semiconductor Reliability Engineer – Advanced Silicon & Packaging
Bristol, UK·Physical Systems
OpenAI3w
Advanced Packaging Multi-Physics Modeling Engineer
San Francisco·Physical Systems
Cerebras Systems3w
Physical Design Engineer
Bengaluru, Karnataka, India·Physical Systems
Block3w
ASIC Validation Engineer
Toronto, Ontario, Canada·Physical Systems
Graphcore1mo
Senior Silicon Logical Design Engineer - Bengaluru
Bengaluru, India·Physical Systems
OpenAI1mo
SOC Architect
San Francisco·Physical Systems
Block1mo
ASIC Validation Engineer
Bay Area, CA, United States of America·Physical Systems
Graphcore1mo
Staff Bring-Up and Characterisation Engineer
Austin, Texas, United States·Physical Systems
Graphcore1mo
Staff Engineer - Server Hardware Compute Blade and Rack Validation Lead
Austin, Texas, United States·Physical Systems
Graphcore1mo
Tech Director, Post Silicon Validation
Bristol, UK·Physical Systems
Graphcore1mo
Staff Engineer - Platform Bring-up and Validation
Austin, Texas, United States·Physical Systems
Graphcore1mo
Senior Bring-Up and Characterisation Engineer
Austin, Texas, United States·Physical Systems